LTC4240
8
4240f
PWRGD (Pin 8): Open-Drain Power Good Output. Con-
nect the CPCI HEALTHY# signal to the PWRGD pin.
PWRGD remains low while V
12VOUT
e 11.1V, V
3VOUT
e
2.9V, V
5VOUT
e 4.65V and V
EEOUT
d 10.5V. When any of
the supplies drops below its power good threshold volt-
age, PWRGD will go high after a 10祍 deglitching time. The
switches will not be turned off when PWRGD goes high,
unless a fault has occurred. The CPCI specification calls
for a 0.01礔 bypass capacitor on the backplane for
HEALTHY#.
BE (Pin 9): QuickSwitch Bus Enable Output. The BE output
remains high until power is good on all supplies. This
serves to isolate the I/O data lines during live
insertion. This is a CMOS output powered by 5V
IN
.
GND (Pin 10): Analog Ground. Connect to analog ground
plane.
ADDRIN (Pin 11): I
2
C Address Programming Input. The
I
2
C address is programmed by connecting the ADDRIN
pin to a resistor divider between the 5V
IN
pin and GND. See
Table 1 for 1% resistor values and corresponding ad-
dresses. Resistors must be placed close to the ADDRIN
pin to minimize errors due to stray capacitance and
resistance on the board trace. Connect this pin to ground
if I
2
C is not used.
SDA (Pin 12): I
2
C Data Input and Output. Note that TTL
levels are used. Connect this pin to ground if I
2
C is not
used.
SCL (Pin 13): I
2
C Clock Input, 100kHz Maximum. Note
that TTL levels are used. Do not float. Connect this pin to
ground if I
2
C is not used.
RESETOUT (Pin 14): Open-Drain Reset Output. Connect
the CPCI LOCAL_PCI_RST# signal to the RESETOUT pin.
RESETOUT is the logical combination of RESETIN, PWRGD,
and I
2
C RESETOUT latch output.
LED (Pin 15): CPCI Status LED. Pulls low to light LED
when RESETOUT is low or when the I
2
C LED latch is set.
DGND (Pin 16): Digital Ground. Connect to ground plane.
DRIVE (Pin 17): External transistors base drive output for
bus precharge. Connects to the base of an external NPN
emitter-follower which in turn biases the PRECHARGE
PRSNT1# (Pin 1): PCI Present Detect Input 1. PRSNT1#
and PRSNT2# are readable over the I
2
C Bus. PRSNT1#
and PRSNT2# indicate the maximum power used by the
card. Do not float.
PRSNT2# (Pin 2): PCI Present Detect Input 2. Do not float.
12V
IN
(Pin 3): 12V Supply Input. A 0.5& switch is inter-
nally connected between 12V
IN
and 12V
OUT
with foldback
current limit. An undervoltage lockout circuit prevents the
switches from turning on while the 12V
IN
pin is below 8V.
12V
IN
provides power to some of the LTC4240s internal
circuitry. See Input Transient Protection section on how to
protect 12V
IN
from large voltage transients.
V
EEIN
(Pin 4): 12V Supply Input. A 1& internal switch is
connected between V
EEIN
and V
EEOUT
with foldback cur-
rent limit. An undervoltage lockout circuit prevents the
switches from turning on while V
EEIN
is above 9V. See
Connecting V
EEIN
section for more notes on V
EEIN
and
V
EEOUT
. Also refer to Input Transient Protection section.
TIMER/AUX 12V
IN
(Pin 5): Current Fault Inhibit Timing
Input. Connect a capacitor from TIMER to GND. With the
LTC4240 turned off (OFF/ON = HIGH), the TIMER pin is
internally held at GND. When the device is turned on, an
11.5礎 pull-up current source is connected to TIMER.
Current limit faults will be ignored until the voltage at the
TIMER pin rises above 5.5V. The Timer capacitor also
serves as an auxiliary charge reservoir for internal V
CC
in
the event the 12V
IN
pin voltage glitches below the LTC4240
UVL threshold voltage.
5V
OUT
(Pin 6): 5V Output Sense. The PWRGD pin will not
pull low until the 5V
OUT
pin voltage exceeds 4.65V. When
the power switches are turned off, a 50& resistor pulls
5V
OUT
to ground.
FAULT (Pin 7): Open-Drain Fault Output . FAULT is pulled
low when a current limit fault is detected. Current limit
faults are ignored until the voltage at the TIMER pin is
above 5.5V. Once the TIMER cycle is complete, FAULT
pulls low and the LTC4240 turns off (in the event of an
overcurrent fault lasting longer than 35祍). The LTC4240
will remain in the off state until the OFF/ON pin is cycled
high then low or power is cycled. Note that the OFF/ON
cycling can also be performed using I
2
C bus.
U
U
PI FU CTIO S
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